In recent years, the operation rate of AD converters (analog-to-digital converters, ADCs) has increased and even operation rates higher than 1 GHz are not rare. However, in high-speed operations, it is difficult for comparators to perform a comparison operation. To enable operation of comparators at high frequencies, it is effective to elongate their operation period by controlling the duty ratio of a clock. Necessary conversion accuracy of AD converters can be maintained in this manner.
For example, an AD converter is known which has a comparator that performs a comparison operation during high periods of a clock (refer to Patent document 1, for example). This AD converter is equipped with a replica circuit of a comparator and a clock synthesis circuit which sets, as a high period of a clock, a period that is for a comparison operation of the replica circuit and sets the remaining period as a low period of the clock.